The invention relates to 3D integrated circuits, and more particularly to structures and methods for suppressing latch-up and noise coupling.
A typical CMOS circuit includes N- and P-type regions arranged to form planar or multi-gate MOS transistors. Regions of opposite conductivity types which are adjacent each other typically form parasitic pn junctions and bipolar transistor structures. While usually reverse-biased, conditions can occur in which these structures become forward biased. When this occurs, a positive feedback loop ensues which provides a low resistance current path from the positive supply voltage to ground, thereby interfering with proper functioning of the circuit and, in serious cases, destroying the chip through heat damage.
FIG. 1 is a schematic diagram showing a typical CMOS arrangement including a PMOS transistor 110 adjacent to an NMOS transistor 112. Such proximity is common in CMOS devices. The PMOS transistor 110 includes two heavily doped P+ diffusion regions 116 and 118 separated laterally by a channel region 120. A gate stack 122 overlies the channel region 120. The two P+ diffusion regions 116 and 118 are formed inside an N-well 124, which is itself an N-doped region formed inside a lightly doped P− substrate 114. Also formed within the N-well 124 is a heavily doped N+ diffusion 125, also called a well tie or a contact pad, for connecting the N-Well 124 to VDD.
The NMOS transistor 112 includes two heavily doped N+ type diffusion regions 126 and 128 separated laterally by a channel region 130. A gate stack 132 overlies the channel region 130. The two N+ diffusion regions 126 and 128 are formed directly in the P− substrate 114. Also formed in the substrate in close proximity to one of the N+ diffusion regions 126 and 128, is a heavily doped P+ diffusion region 135, also called a substrate tie or a contact pad, for connecting the P− substrate 114 to ground.
Other CMOS arrangements are common as well, including those that also include a lightly doped P−-well in which the NMOS transistor 112 is formed. The arrangement of FIG. 1 will be illustrative of the latch-up problem, but it will be understood that many other arrangements also suffer from the same problem.
Superimposed on the CMOS diagram of FIG. 1 is a circuit schematic illustrating the bipolar transistors that are formed by the various PN junctions formed by the CMOS arrangement. In particular, a PNP transistor Q1 is formed by one of the P+ diffusions 116 or 118 acting as the emitter E1, the N-well 124 acting as the base B1, and the P− substrate 114 acting as the collector C1. At the same time, the N-well 124 acts as the collector C2 of an NPN transistor Q2, with the P− substrate 114 acting as the base B2, and one of the N+ regions 126 or 128 acting as the emitter E2. The base B1 of the PNP transistor Q1 is connected to the collector C2 of the NPN transistor Q2, and the base of NPN transistor Q2 is connected to the collector C1 of PNP transistor Q1. The base B1 of transistor Q1 is connected to N+ diffusion 125 through the resistance Rw of the N-well 124, and the base B2 of transistor Q2 is connected to P+ diffusion 135 through the substrate resistance Rs.
FIG. 2 is schematic circuit diagram of FIG. 1 rearranged to show it vertically. It can be seen that as long as the two bipolar transistors Q1 and Q2 are not forward biased, current will not flow through the circuit. A number of conditions can trigger latch-up however, including noise, which sometimes can induce sufficient current at the base of one of the transistors for long enough to forward bias the other transistor, thereby starting a feedback loop. Several techniques have been devised for reducing or eliminating latch-up susceptibility, some of which are discussed in Wolf, Silicon Processing for the VLSI Era, Vol. II, Process Integration, pp. 400-419 (1990), incorporated herein by reference.
One common technique for reducing or eliminating latch-up susceptibility is to connect the backside of the substrate to ground. Referring to FIG. 1, if the substrate is connected to ground through an additional one or more ties such as substrate back-tie in addition to tie 135 which is also connected to ground, it can be seen that this technique provides a low resistance current path in parallel with the substrate resistance Rs, effectively short circuiting it. The base B2 of NPN transistor Q2 therefore is effectively connected to its emitter E2 and the transistor cannot conduct.
FIG. 3 (consisting of FIGS. 3A and 3B) illustrates how the short circuiting of Rs is often accomplished in a typical lead frame package. FIG. 3A is a cross-sectional view of the package showing a die 310, and FIG. 3B is an enlarged topside view of a corner 322 of the structure of FIG. 3A. As shown in FIG. 3A, the die 310 is attached on its back side using an electrically conductive die attach adhesive 312, to a metal lead frame pad 314. The lead frame also includes a number of metal leads 316 that extend out through the epoxy molded packaging material 318 for external electrical connection. Some of the leads 316, for example lead 316A, are connected to the lead frame pad 314 to ground externally of the package, and thereby connect the back side of the die 310 to ground. Others of the leads 316 are connected to various I/O and power pads (324 in FIG. 3B) on the top side of the chip. In addition, FIG. 3B also illustrates that some of the bonding pads 324, for example 324A, are connected (“down-bonded”) directly to the lead frame pad 314 using corresponding bonding wires 320A. These bonding pads 324A are formed on and connect to heavily doped P+ contact pads such as 135 (FIG. 1). Since as previously mentioned the backside of the die is also connected to the lead frame pad 314 through conductive die attach material 312, it can be seen that a very low resistance conductive path is formed electrically connecting the P+ contact pads 135 to the backside of the substrate die 310, thereby short circuiting the substrate resistance Rs (FIG. 1). With Rs short circuited, it becomes much less likely that transient current flow through PNP transistor Q1 can increase the base-collector voltage on NPN transistor Q2 sufficiently to turn it on. As a result, latch-up conditions are less likely.
Recently, as integrated circuit densities have increased, manufacturers have begun developing packaging structures in which two or more dies are stacked on top of each other. Signal and power supply lines from the top surface of one chip are passed through the body of the chip to the one below using through-silicon vias (TSVs). A TSV is a conductive post that extends all the way through the chip, from the topside surface to the backside surface, where it can connect through metal bump contacts to conductors on the topside surface of the below-adjacent chip. The conductor in the TSV is typically copper or another metal such as TiW, and it is typically isolated from the substrate along its entire length by a dielectric or other barrier material. On the topside, ordinary metal interconnects connect the top ends of the TSV conductors to circuit components. The backside surface of the chip is coated with an insulator, such as an oxide, and holes are opened to expose the bottom ends of the TSV conductors. One or more layers of metal interconnects (called RDL (redistribution layer) conductors) are formed on the backside to electrically route signals and power from the bottom ends of the TSV conductors to the positions required for mating with the appropriate bump contacts on the below-adjacent chip. The bottom chip in the stack is connected to external circuitry usually by TSVs connected on the backside to a ball grid array (BGA). The overall stack of chips is sometimes referred to herein as a three-dimensional integrated circuit (3DIC).
3DIC technology poses a number of problems for known techniques for suppressing latch-up. First, because of the difficulties in fabricating very deep TSVs, chip substrates used in 3DICs typically are considerably thinned, from the backside, to a thickness of only around 50 microns. Referring to FIG. 1, it can be seen that a much thinner substrate considerably narrows the current path through the substrate to the P+ substrate contact pads 135, thereby significantly increasing the substrate resistance Rs. Moreover, down-bonding is no longer available to short circuit this current path, since the substrate backside is not connected by die attach adhesive to a below-adjacent lead frame pad. Thus Rs is not short circuited, and the potential for latch-up conditions is significantly higher. Second, in 3DIC's, it is common for TSVs to be used to carry power and signals through a particular chip, from the below-adjacent chip to the above-adjacent chip and vice-versa, without ever having to connect to the chip or chips stacked between them. This is common where, for example, some chips are designed to operate at 1 volt while the chips above and below are operating at 3.3 volts. In this case the TSV might carry a 3.3 volt signal through a 1 volt chip, which can easily induce sufficient currents by capacitive coupling to trigger latch-up in the more sensitive 1 volt chip.
Accordingly, an opportunity arises to create robust solutions to the problem of latch-up susceptibility in 3D integrated circuits. Better chip yields, and denser, and more powerful circuits, components and systems may result.